Digital Trainer to Verify Adders and Sub-tractor using NAND Gates
Product Code : JA-DEECP-1171
The Digital Trainer to Verify Adders and Sub-tractor using NAND Gates (SKU JA-DEECP-1171) covers four arithmetic circuits: half adder, half subtractor, full adder and full subtractor. Each is built from NAND gates only, which shows the NAND gate as a universal gate able to produce the XOR, AND and OR functions these circuits need. Students verify each truth table against the expected sum, difference, carry and borrow.
Specifications
The listing gives the circuits only:
| Product | Digital Trainer to Verify Adders and Sub-tractor using NAND Gates |
| SKU | JA-DEECP-1171 |
| Circuits | Half adder, half subtractor, full adder, full subtractor |
| Gates | NAND gates only |
| Inputs, indicators and supply | Confirmed on the quotation |
Scope of supply and ordering
Supply, input and indicator details, quantities and packing are stated on the quotation.
Frequently asked questions
Which circuits can be verified on the NAND gate trainer?
Half adder, half subtractor, full adder and full subtractor.
Why use NAND gates only?
NAND is a universal gate, so every function in these circuits can be built from it alone.
Related products
- Digital Trainer to Verify Half Adder using OR, EX-OR and AND Gates
- Digital Trainer to Verify Full Adder using OR, EX-OR and AND Gates
- Digital Trainer to Verify Full Subtractor using OR, EX-OR and AND Gates
- Logic Gate Circuit Trainer using TTL IC
More digital trainers are listed in our scientific instrument range.
Request a quote
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